1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit, and more particularly, to a charge pump in a PLL circuit.
2. Description of the Related Art
A phase-locked loop (PLL) which in general is a circuit for restoring a clock signal used to modulate or encode an input signal, is used in various applications such as demodulation of a frequency-modulated (FM) signal or a stereo signal, or restoring a signal recorded on a recording medium.
FIG. 1 contains a block diagram of a typical charge pump type PLL circuit. In the PLL circuit of FIG. 1, a phase detector 2 receives a reference signal and detects the phase difference between the reference signal and a signal output from a divider 10. The phase detector 2 outputs a digital voltage, i.e., an up signal UP or a down signal DN, in accordance with the difference in the detected phase. The charge pump 4 outputs analog pumping current I.sub.pump in accordance with the digital voltage from the phase detector 2. A loop filter 6 receives the pumping current I.sub.pump, and charges and discharges an internal capacitor in accordance with the pumping current to low-pass filter the pumping current, so that a filtered voltage is output as a control voltage. A voltage controlled oscillator (VCO) 8 receives the control voltage and produces an oscillation signal having a frequency corresponding to the control voltage. The divider 10 is selectively used and divides the oscillation signal output from the VCO 8 to output the divided signal to the phase detector 2.
In a clock recovery PLL for recovering a non return-to-zero (NRZ) type clock signal, a Hogge Phase Detector is typically used. FIG. 2 shows an example of signals in a PLL employing the Hogge Phase Detector. Assuming that the input reference signal and the divided oscillation signal have waveforms as shown in FIGS. 2A and 2B, respectively, the up signal UP is a pulse signal having a rising edge at the rising edge of the reference signal and a falling edge at the rising edge of the divided oscillation signal, as shown in FIG. 2C. Also, as shown in FIG. 2D, the down signal DN is a pulse signal having a rising edge at the rising edge of the divided oscillation signal and a falling edge at the falling edge of the divided oscillation signal. In this case, the VCO control signal output from the loop filter 6 has a waveform as shown in FIG. 2E.
If the levels of the pumping currents I.sub.pump according to the up and the down signals UP and DN are the same, and the reference signal and the divided oscillation signal are in phase, the rising edge or the falling edge of the divided oscillation signal is accurately matched with the rising edge of the reference signal as shown in FIGS. 2A and 2B. Also, as shown in FIGS. 2C and 2D, the up and down signals UP and DN have the same pulse widths. Thus, charge stored in the loop filter 6 is maintained by a predetermined pattern, so that there is no change in the VCO control voltage.
However, if the levels of the pumping currents I.sub.pump according to the up and down signals UP and DN are different, pulse widths of the up and down signals UP and DN are different, as shown in FIGS. 3C and 3D. Also, when the phase is locked, a phase error in which the falling edge of the oscillation signal is mismatched with the rising edge of the reference signal is generated as shown in FIGS. 3A and 3B. Here, if the input signal has jitter, a circuit which demodulates data using the restored clock signal has a high probability of generating errors. FIG. 4A shows a reference signal including jitter, FIG. 4B shows an oscillation signal having phase error, and FIG. 4C shows the bit error rate according to the phase error. If the pumping currents I.sub.pump according to the up and down signals UP and DN are different, the jitter tolerance is lowered, thereby increasing the bit error rate.
If a capture range of the PLL or a lock range thereof is large, the frequency range of the input reference voltage is large, as in, for example, the PLL employed for a CD-ROM system or a DVD-ROM system, so that the current offset becomes more severe. For instance, a 24.times. speed ROM must operate at 16.times. speed, 8.times. speed, or less, in accordance with the stored information and the state of the CD-ROM, and thus the frequency range of the reference voltage input to the PLL is large. Also, if a spindle motor is controlled such that the CD-ROM or the DVD-ROM rotates at a constant angular velocity (CAV), the frequency range of the reference voltage is increased.
As described above, it is very important that in the charge pump the levels of the pumping currents I.sub.pump in response to the up signal UP and the down signal DN are equalized. Thus, various methods for equalizing current and reducing static phase error in the charge pump have been proposed. One of them is disclosed in U.S. Pat. No. 5,646,563 assigned to National Semiconductor Corporation, entitled, "Charge Pump with Near Zero Offset Current."
In the conventional approaches, although current matching is improved, the current cannot be completely, i.e., 100% matched. This is because the current in a saturation mode varies in accordance with a gate-source voltage V.sub.GS or a base-emitter voltage V.sub.BE of a transistor, instead of having a constant level. Also, even if the current is completely matched, the electric potential of the VCO control voltage can change when the widths of the up signal UP and the down signal DN output from a phase detector are the same. This is because delay paths in which the up signal UP and the down signal DN output from the phase detector operate in the charge pump may be different in the layout level stage, and switches opened and closed by the signals have various characteristics. Also, since distributions of current levels are different in processes, it is difficult to equalize two currents in the charge pump with each other.